| 67 | | // Configure SPI Control Register (SPCR) (All values initially 0) |
| 68 | | // Bit Description |
| 69 | | // 7 SPI Interrupt Enable -- disable (SPIE --> 0) |
| 70 | | // 6 SPI Enable -- enable (SPE --> 1) |
| 71 | | // 5 Data Order -- MSB 1st (DORD --> 0) (Slave specific) |
| 72 | | // 4 Master/Slave Select -- master (MSTR --> 1) |
| 73 | | // 3 Clock Polarity -- (CPOL --> 0) (Slave specific) ("Mode") |
| 74 | | // 2 Clock Phase -- (CPHA --> 0) (Slave specific) |
| 75 | | // 1 SPI Clock Rate Select 1 -- } (SPR1 --> 0) |
| 76 | | // 0 SPI Clock Rate Select 0 -- } fOSC/4 (SPR0 --> 0) ("Fastest" but see SPI2X in SPSR) |
| | 67 | /* |
| | 68 | Configure SPI Control Register (SPCR) (All values initially 0) |
| | 69 | Bit Description |
| | 70 | 7 SPI Interrupt Enable -- disable (SPIE --> 0) |
| | 71 | 6 SPI Enable -- enable (SPE --> 1) |
| | 72 | 5 Data Order -- MSB 1st (DORD --> 0) (Slave specific) |
| | 73 | 4 Master/Slave Select -- master (MSTR --> 1) |
| | 74 | 3 Clock Polarity -- (CPOL --> 0) (Slave specific) ("Mode") |
| | 75 | 2 Clock Phase -- (CPHA --> 0) (Slave specific) |
| | 76 | 1 SPI Clock Rate Select 1 -- } (SPR1 --> 0) |
| | 77 | 0 SPI Clock Rate Select 0 -- } fOSC/4 (SPR0 --> 0) ("Fastest" but see SPI2X in SPSR) |
| | 78 | */ |
