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w5100.c

Revision 140, 33.5 KB (checked in by follower, 11 months ago)
Add author, license and copyright details. (Which weren't permitted in competition entry source.)

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1	/*
2
3	@file w5100.c
4
5	Original Author:
6
7	WIZnet Inc.
8
9	Modifications by:
10
11	Philip Lindsay <follower@rancidbacon.com>
12
13	Modifications license:
14
15	Copyright 2007-2008 // LGPL
16
17	*/
18
19	#include <stdio.h>
20	#include <string.h>
21
22	#include <avr/interrupt.h>
23	// #include <avr/io.h>
24
25	#include "types.h"
26
27	#include "w5100.h"
28
29
30
31	#ifdef __DEF_IINCHIP_PPP__
32	#include "md5.h"
33	#include "delay.h" // for wait function
34	#endif
35
36	static uint8 I_STATUS[MAX_SOCK_NUM];
37	static uint16 SMASK[MAX_SOCK_NUM]; /*< Variable for Tx buffer MASK in each channel /
38	static uint16 RMASK[MAX_SOCK_NUM]; /*< Variable for Rx buffer MASK in each channel /
39	static uint16 SSIZE[MAX_SOCK_NUM]; /*< Max Tx buffer size by each channel /
40	static uint16 RSIZE[MAX_SOCK_NUM]; /*< Max Rx buffer size by each channel /
41	static uint16 SBUFBASEADDRESS[MAX_SOCK_NUM]; /*< Tx buffer base address by each channel /
42	static uint16 RBUFBASEADDRESS[MAX_SOCK_NUM]; /*< Rx buffer base address by each channel /
43
44	uint8 getISR(uint8 s)
45	{
46	return I_STATUS[s];
47	}
48
49	void putISR(uint8 s, uint8 val)
50	{
51	I_STATUS[s] = val;
52	}
53
54	uint16 getIINCHIP_RxMAX(uint8 s)
55	{
56	return RSIZE[s];
57	}
58	uint16 getIINCHIP_TxMAX(uint8 s)
59	{
60	return SSIZE[s];
61	}
62	uint16 getIINCHIP_RxMASK(uint8 s)
63	{
64	return RMASK[s];
65	}
66	uint16 getIINCHIP_TxMASK(uint8 s)
67	{
68	return SMASK[s];
69	}
70	uint16 getIINCHIP_RxBASE(uint8 s)
71	{
72	return RBUFBASEADDRESS[s];
73	}
74	uint16 getIINCHIP_TxBASE(uint8 s)
75	{
76	return SBUFBASEADDRESS[s];
77	}
78
79	/**
80	@brief This function writes the data into W5100 registers.
81	*/
82	uint8 IINCHIP_WRITE(uint16 addr,uint8 data)
83	{
84	// DIRECT MODE I/F
85	#if (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_DIRECT_MODE__)
86	IINCHIP_ISR_DISABLE();
87	((vuint8)(addr)) = data;
88	IINCHIP_ISR_ENABLE();
89	#elif(__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_INDIRECT_MODE__) /* INDIRECT MODE I/F */
90	IINCHIP_ISR_DISABLE();
91	((vuint8)IDM_AR0) = (uint8)((addr & 0xFF00) >> 8);
92	((vuint8)IDM_AR1) = (uint8)(addr & 0x00FF);
93	((vuint8)IDM_DR) = data;
94	IINCHIP_ISR_ENABLE();
95	#elif (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_SPI_MODE__)
96	//SPI MODE I/F
97	IINCHIP_ISR_DISABLE();
98	#ifndef __ARDUINO__
99	DDRB = 0x07; // MISO=input, etc.=output
100	// PB3(MISO), PB2(MOSI), PB1(SCK), PB0(/SS)
101	PORTB = 0x01; // CS=1, waiting for SPI start
102	SPCR = 0x50; // SPI mode 0, 4MHz
103	SPSR = 0x01; // SPI2X=0
104
105	PORTB = 0x00; // CS=0, SPI start
106	#else
107	PORTB = PORTB & ~CS_PIN; // CS=0, SPI start
108	#endif // ifndef __ARDUINO__
109	SPDR = 0xF0;
110	while((SPSR&0x80)==0x00);
111	SPDR = (uint8)((addr & 0xFF00) >> 8);
112	while((SPSR&0x80)==0x00);
113	SPDR = (uint8)(addr & 0x00FF);
114	while((SPSR&0x80)==0x00);
115	SPDR = data;
116	while((SPSR&0x80)==0x00);
117	#ifndef __ARDUINO__
118	PORTB = 0x01; // SPI end
119	// CS=1, waiting for SPI start
120	#else
121	PORTB = PORTB \| CS_PIN; // SPI end
122	#endif // ifndef __ARDUINO__
123	IINCHIP_ISR_ENABLE();
124	#else
125	#error "unknown bus type"
126	#endif
127	return 1;
128	}
129
130
131	/**
132	@brief This function reads the value from W5100 registers.
133	*/
134	uint8 IINCHIP_READ(uint16 addr)
135	{
136	uint8 data;
137
138	// DIRECT MODE I/F
139
140	#if (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_DIRECT_MODE__)
141	IINCHIP_ISR_DISABLE();
142	data = ((vuint8)(addr));
143	IINCHIP_ISR_ENABLE();
144	#elif(__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_INDIRECT_MODE__)
145	IINCHIP_ISR_DISABLE();
146	((vuint8)IDM_AR0) = (uint8)((addr & 0xFF00) >> 8);
147	((vuint8)IDM_AR1) = (uint8)(addr & 0x00FF);
148	data = ((vuint8)IDM_DR);
149	IINCHIP_ISR_ENABLE();
150
151	#elif (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_SPI_MODE__)
152	//SPI MODE I/F
153	IINCHIP_ISR_DISABLE();
154	#ifndef __ARDUINO__
155	DDRB = 0x07; // MISO=input, etc.=output
156	// PB3(MISO), PB2(MOSI), PB1(SCK), PB0(/SS)
157	PORTB = 0x01; // CS=1, waiting for SPI start
158	SPCR = 0x50; // SPI mode 0, 4MHz
159	SPSR = 0x01; // SPI2X=0
160
161	PORTB = 0x00; // CS=0, SPI start
162	#else
163	PORTB = PORTB & ~CS_PIN; // CS=0, SPI start
164	#endif // ifndef __ARDUINO__
165	SPDR = 0x0F;
166	while((SPSR&0x80)==0x00);
167	SPDR = (uint8)((addr & 0xFF00) >> 8);
168	while((SPSR&0x80)==0x00);
169	SPDR = (uint8)(addr & 0x00FF);
170	while((SPSR&0x80)==0x00);
171	SPDR = 0x00; // write dummy data
172	while((SPSR&0x80)==0x00);
173	data = SPDR; // read data
174	#ifndef __ARDUINO__
175	PORTB = 0x01; // SPI end
176	// CS=1, waiting for SPI start
177	#else
178	PORTB = PORTB \| CS_PIN; // SPI end
179	#endif // ifndef __ARDUINO__
180	IINCHIP_ISR_ENABLE();
181	#else
182	#error "unknown bus type"
183	#endif
184	return data;
185	}
186
187
188	/**
189	@brief This function writes into W5100 memory(Buffer)
190	*/
191	uint16 wiz_write_buf(uint16 addr,uint8* buf,uint16 len)
192	{
193	#if (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_DIRECT_MODE__)
194	IINCHIP_ISR_DISABLE();
195	memcpy((uint8 *)addr, buf, len);
196	IINCHIP_ISR_ENABLE();
197	#elif (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_INDIRECT_MODE__)
198	uint16 idx = 0;
199	IINCHIP_ISR_DISABLE();
200	((vuint8)IDM_AR0) = (uint8)((addr & 0xFF00) >> 8);
201	((vuint8)IDM_AR1) = (uint8)(addr & 0x00FF);
202	for (idx = 0; idx < len ; idx++) ((vuint8)IDM_DR) = buf[idx];
203	IINCHIP_ISR_ENABLE();
204	#elif (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_SPI_MODE__)
205	//SPI MODE I/F
206	IINCHIP_ISR_DISABLE();
207	uint16 ii=0;
208
209	for(ii=0;ii<len;ii++)
210	{
211	#ifndef __ARDUINO__
212	DDRB = 0x07; // MISO=input, etc.=output
213	// PB3(MISO), PB2(MOSI), PB1(SCK), PB0(/SS)
214	PORTB = 0x01; // CS=1, waiting for SPI start
215	SPCR = 0x50; // SPI mode 0, 4MHz
216	SPSR = 0x01; // SPI2X=0
217
218	PORTB = 0x00; // CS=0, SPI start
219	#else
220	PORTB = PORTB & ~CS_PIN; // CS=0, SPI start
221	#endif // ifndef __ARDUINO__
222	SPDR = 0xF0;
223	while((SPSR&0x80)==0x00);
224	SPDR = (uint8)(((addr+ii) & 0xFF00) >> 8);
225	while((SPSR&0x80)==0x00);
226	SPDR = (uint8)((addr+ii) & 0x00FF);
227	while((SPSR&0x80)==0x00);
228	SPDR = buf[ii];
229	while((SPSR&0x80)==0x00);
230	#ifndef __ARDUINO__
231	PORTB = 0x01; // SPI end
232	// CS=1, waiting for SPI start
233	#else
234	PORTB = PORTB \| CS_PIN; // SPI end
235	#endif // ifndef __ARDUINO__
236	}
237	IINCHIP_ISR_ENABLE();
238	#else
239	#error "unknown bus type"
240	#endif
241	return len;
242	}
243
244
245	/**
246	@brief This function reads into W5100 memory(Buffer)
247	*/
248	uint16 wiz_read_buf(uint16 addr, uint8* buf,uint16 len)
249	{
250	#if (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_DIRECT_MODE__)
251	IINCHIP_ISR_DISABLE();
252	memcpy(buf, (uint8 *)addr, len);
253	IINCHIP_ISR_ENABLE();
254	#elif(__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_INDIRECT_MODE__)
255	uint16 idx = 0;
256	IINCHIP_ISR_DISABLE();
257	((vuint8)IDM_AR0) = (uint8)((addr & 0xFF00) >> 8);
258	((vuint8)IDM_AR1) = (uint8)(addr & 0x00FF);
259	for (idx = 0; idx < len ; idx++) buf[idx] = ((vuint8)IDM_DR);
260	IINCHIP_ISR_ENABLE();
261	#elif (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_SPI_MODE__)
262	//SPI MODE I/F
263	IINCHIP_ISR_DISABLE();
264	uint16 iii=0;
265	for (iii=0; iii<len; iii++)
266	{
267	#ifndef __ARDUINO__
268	DDRB = 0x07; // MISO=input, etc.=output
269	// PB3(MISO), PB2(MOSI), PB1(SCK), PB0(/SS)
270	PORTB = 0x01; // CS=1, waiting for SPI start
271	SPCR = 0x50; // SPI mode 0, 4MHz
272	SPSR = 0x01; // SPI2X=0
273
274	PORTB = 0x00; // CS=0, SPI start
275	#else
276	PORTB = PORTB & ~CS_PIN; // CS=0, SPI start
277	#endif // ifndef __ARDUINO__
278	SPDR = 0x0F;
279	while((SPSR&0x80)==0x00);
280	SPDR = (uint8)(((addr+iii) & 0xFF00) >> 8);
281	while((SPSR&0x80)==0x00);
282	SPDR = (uint8)((addr+iii) & 0x00FF);
283	while((SPSR&0x80)==0x00);
284	//for (iii=0; iii<len; iii++)
285	//{
286	SPDR = 0x00; // write dummy data
287	while((SPSR&0x80)==0x00);
288	buf[iii]=SPDR; // read data
289	//}
290	#ifndef __ARDUINO__
291	PORTB = 0x01; // SPI end
292	// CS=1, waiting for SPI start
293	#else
294	PORTB = PORTB \| CS_PIN; // SPI end
295	#endif // ifndef __ARDUINO__
296	}
297	IINCHIP_ISR_ENABLE();
298	#else
299	#error "unknown bus type"
300	#endif
301	return len;
302	}
303
304	#ifndef __ARDUINO__
305	#if (__COMPILER_VERSION__ == __WINAVR_20050214__)
306	static void iinchip_irq(void);
307
308	void SIG_INTERRUPT4( void ) __attribute__ ((signal));
309	void SIG_INTERRUPT4( void )
310	{
311	iinchip_irq();
312	}
313
314
315	/**
316	@brief Socket interrupt routine
317	*/
318	static void iinchip_irq(void)
319	{
320	#ifdef __DEF_IINCHIP_INT__
321	uint8 int_val;
322	IINCHIP_ISR_DISABLE();
323	int_val = IINCHIP_READ(IR);
324
325	if (int_val & IR_CONFLICT)
326	{
327	printf("IP conflict : %.2x\r\n", int_val);
328	}
329	if (int_val & IR_UNREACH)
330	{
331	printf("INT Port Unreachable : %.2x\r\n", int_val);
332	printf("UIPR0 : %d.%d.%d.%d\r\n", IINCHIP_READ(UIPR0), IINCHIP_READ(UIPR0+1), IINCHIP_READ(UIPR0+2), IINCHIP_READ(UIPR0+3));
333	printf("UPORT0 : %.2x %.2x\r\n", IINCHIP_READ(UPORT0), IINCHIP_READ(UPORT0+1));
334	}
335
336	if (int_val & IR_SOCK(0))
337	{
338	I_STATUS[0] = IINCHIP_READ(Sn_IR(0));
339	IINCHIP_WRITE(Sn_IR(0), I_STATUS[0] & 0xf);
340	}
341	if (int_val & IR_SOCK(1))
342	{
343	I_STATUS[1] = IINCHIP_READ(Sn_IR(1));
344	IINCHIP_WRITE(Sn_IR(1), I_STATUS[1] & 0xf);
345	}
346	if (int_val & IR_SOCK(2))
347	{
348	I_STATUS[2] = IINCHIP_READ(Sn_IR(2));
349	IINCHIP_WRITE(Sn_IR(2), I_STATUS[2] & 0xf);
350	}
351	if (int_val & IR_SOCK(3))
352	{
353	I_STATUS[3] = IINCHIP_READ(Sn_IR(3));
354	IINCHIP_WRITE(Sn_IR(3), I_STATUS[3] & 0xf);
355	}
356
357	IINCHIP_WRITE(IR, int_val);
358
359	IINCHIP_ISR_ENABLE();
360
361	#endif
362	}
363	#else
364	/**
365	@brief Socket interrupt routine
366	*/
367	ISR(INT4_vect)
368	{
369	#ifdef __DEF_IINCHIP_INT__
370	uint8 int_val;
371	IINCHIP_ISR_DISABLE();
372	int_val = IINCHIP_READ(IR);
373
374	if (int_val & IR_CONFLICT)
375	{
376	printf("IP conflict : %.2x\r\n", int_val);
377	}
378	if (int_val & IR_UNREACH)
379	{
380	printf("INT Port Unreachable : %.2x\r\n", int_val);
381	printf("UIPR0 : %d.%d.%d.%d\r\n", IINCHIP_READ(UIPR0), IINCHIP_READ(UIPR0+1), IINCHIP_READ(UIPR0+2), IINCHIP_READ(UIPR0+3));
382	printf("UPORT0 : %.2x %.2x\r\n", IINCHIP_READ(UPORT0), IINCHIP_READ(UPORT0+1));
383	}
384
385	if (int_val & IR_SOCK(0))
386	{
387	I_STATUS[0] = IINCHIP_READ(Sn_IR(0));
388	IINCHIP_WRITE(Sn_IR(0), I_STATUS[0] & 0xf);
389	}
390	if (int_val & IR_SOCK(1))
391	{
392	I_STATUS[1] = IINCHIP_READ(Sn_IR(1));
393	IINCHIP_WRITE(Sn_IR(1), I_STATUS[1] & 0xf);
394	}
395	if (int_val & IR_SOCK(2))
396	{
397	I_STATUS[2] = IINCHIP_READ(Sn_IR(2));
398	IINCHIP_WRITE(Sn_IR(2), I_STATUS[2] & 0xf);
399	}
400	if (int_val & IR_SOCK(3))
401	{
402	I_STATUS[3] = IINCHIP_READ(Sn_IR(3));
403	IINCHIP_WRITE(Sn_IR(3), I_STATUS[3] & 0xf);
404	}
405
406	IINCHIP_WRITE(IR, int_val);
407
408	IINCHIP_ISR_ENABLE();
409
410	#endif
411	}
412	#endif
413	#endif // ifndef __ARDUINO__
414
415	/**
416	@brief This function is for resetting of the iinchip. Initializes the iinchip to work in whether DIRECT or INDIRECT mode
417	*/
418	void iinchip_init(void)
419	{
420	setMR(MR_RST);
421
422	#if (__DEF_IINCHIP_BUS__ == __DEF_IINCHIP_INDIRECT_MODE__)
423	setMR(MR_IND \| MR_AI);
424	#ifdef __DEF_IINCHIP_DBG__
425	printf("MR value is %d \r\n",IINCHIP_READ(MR));
426	#endif
427	#endif
428	}
429
430
431	/**
432	@brief This function set the transmit & receive buffer size as per the channels is used
433
434	Note for TMSR and RMSR bits are as follows\n
435	bit 1-0 : memory size of channel #0 \n
436	bit 3-2 : memory size of channel #1 \n
437	bit 5-4 : memory size of channel #2 \n
438	bit 7-6 : memory size of channel #3 \n\n
439	Maximum memory size for Tx, Rx in the W5100 is 8K Bytes,\n
440	In the range of 8KBytes, the memory size could be allocated dynamically by each channel.\n
441	Be attentive to sum of memory size shouldn't exceed 8Kbytes\n
442	and to data transmission and receiption from non-allocated channel may cause some problems.\n
443	If the 8KBytes memory is already assigned to centain channel, \n
444	other 3 channels couldn't be used, for there's no available memory.\n
445	If two 4KBytes memory are assigned to two each channels, \n
446	other 2 channels couldn't be used, for there's no available memory.\n
447	*/
448	void sysinit(
449	uint8 tx_size, /*< tx_size Tx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) /
450	uint8 rx_size /*< rx_size Rx memory size (00 - 1KByte, 01- 2KBtye, 10 - 4KByte, 11 - 8KByte) /
451	)
452	{
453	int16 i;
454	int16 ssum,rsum;
455
456	#ifdef __DEF_IINCHIP_DBG__
457	printf("sysinit()\r\n");
458	#endif
459
460	ssum = 0;
461	rsum = 0;
462
463	IINCHIP_WRITE(TMSR,tx_size); /* Set Tx memory size for each channel */
464	IINCHIP_WRITE(RMSR,rx_size); /* Set Rx memory size for each channel */
465
466	SBUFBASEADDRESS[0] = (uint16)(__DEF_IINCHIP_MAP_TXBUF__); /* Set base address of Tx memory for channel #0 */
467	RBUFBASEADDRESS[0] = (uint16)(__DEF_IINCHIP_MAP_RXBUF__); /* Set base address of Rx memory for channel #0 */
468
469	#ifdef __DEF_IINCHIP_DBG__
470	printf("Channel : SEND MEM SIZE : RECV MEM SIZE\r\n");
471	#endif
472
473	for (i = 0 ; i < MAX_SOCK_NUM; i++) // Set the size, masking and base address of Tx & Rx memory by each channel
474	{
475	SSIZE[i] = (int16)(0);
476	RSIZE[i] = (int16)(0);
477	if (ssum < 8192)
478	{
479	switch((tx_size >> i*2) & 0x03) // Set Tx memory size
480	{
481	case 0:
482	SSIZE[i] = (int16)(1024);
483	SMASK[i] = (uint16)(0x03FF);
484	break;
485	case 1:
486	SSIZE[i] = (int16)(2048);
487	SMASK[i] = (uint16)(0x07FF);
488	break;
489	case 2:
490	SSIZE[i] = (int16)(4096);
491	SMASK[i] = (uint16)(0x0FFF);
492	break;
493	case 3:
494	SSIZE[i] = (int16)(8192);
495	SMASK[i] = (uint16)(0x1FFF);
496	break;
497	}
498	}
499	if (rsum < 8192)
500	{
501	switch((rx_size >> i*2) & 0x03) // Set Rx memory size
502	{
503	case 0:
504	RSIZE[i] = (int16)(1024);
505	RMASK[i] = (uint16)(0x03FF);
506	break;
507	case 1:
508	RSIZE[i] = (int16)(2048);
509	RMASK[i] = (uint16)(0x07FF);
510	break;
511	case 2:
512	RSIZE[i] = (int16)(4096);
513	RMASK[i] = (uint16)(0x0FFF);
514	break;
515	case 3:
516	RSIZE[i] = (int16)(8192);
517	RMASK[i] = (uint16)(0x1FFF);
518	break;
519	}
520	}
521	ssum += SSIZE[i];
522	rsum += RSIZE[i];
523
524	if (i != 0) // Sets base address of Tx and Rx memory for channel #1,#2,#3
525	{
526	SBUFBASEADDRESS[i] = SBUFBASEADDRESS[i-1] + SSIZE[i-1];
527	RBUFBASEADDRESS[i] = RBUFBASEADDRESS[i-1] + RSIZE[i-1];
528	}
529	#ifdef __DEF_IINCHIP_DBG__
530	printf("%d : %.4x : %.4x : %.4x : %.4x\r\n", i, (uint16)SBUFBASEADDRESS[i], (uint16)RBUFBASEADDRESS[i], SSIZE[i], RSIZE[i]);
531	#endif
532	}
533	}
534
535	void setMR(uint8 val)
536	{
537	((volatile uint8)(MR)) = val;
538	}
539
540
541	/**
542	@brief This function sets up gateway IP address.
543	*/
544	void setGAR(
545	uint8 * addr /*< a pointer to a 4 -byte array responsible to set the Gateway IP address. /
546	)
547	{
548	IINCHIP_WRITE((GAR0 + 0),addr[0]);
549	IINCHIP_WRITE((GAR0 + 1),addr[1]);
550	IINCHIP_WRITE((GAR0 + 2),addr[2]);
551	IINCHIP_WRITE((GAR0 + 3),addr[3]);
552	}
553	void getGWIP(uint8 * addr)
554	{
555	addr[0] = IINCHIP_READ((GAR0 + 0));
556	addr[1] = IINCHIP_READ((GAR0 + 1));
557	addr[2] = IINCHIP_READ((GAR0 + 2));
558	addr[3] = IINCHIP_READ((GAR0 + 3));
559	}
560
561
562	/**
563	@brief It sets up SubnetMask address
564	*/
565	void setSUBR(
566	uint8 * addr /*< a pointer to a 4 -byte array responsible to set the SubnetMask address /
567	)
568	{
569	IINCHIP_WRITE((SUBR0 + 0),addr[0]);
570	IINCHIP_WRITE((SUBR0 + 1),addr[1]);
571	IINCHIP_WRITE((SUBR0 + 2),addr[2]);
572	IINCHIP_WRITE((SUBR0 + 3),addr[3]);
573	}
574
575
576	/**
577	@brief This function sets up MAC address.
578	*/
579	void setSHAR(
580	uint8 * addr /*< a pointer to a 6 -byte array responsible to set the MAC address. /
581	)
582	{
583	IINCHIP_WRITE((SHAR0 + 0),addr[0]);
584	IINCHIP_WRITE((SHAR0 + 1),addr[1]);
585	IINCHIP_WRITE((SHAR0 + 2),addr[2]);
586	IINCHIP_WRITE((SHAR0 + 3),addr[3]);
587	IINCHIP_WRITE((SHAR0 + 4),addr[4]);
588	IINCHIP_WRITE((SHAR0 + 5),addr[5]);
589	}
590
591
592	/**
593	@brief This function sets up Source IP address.
594	*/
595	void setSIPR(
596	uint8 * addr /*< a pointer to a 4 -byte array responsible to set the Source IP address. /
597	)
598	{
599	IINCHIP_WRITE((SIPR0 + 0),addr[0]);
600	IINCHIP_WRITE((SIPR0 + 1),addr[1]);
601	IINCHIP_WRITE((SIPR0 + 2),addr[2]);
602	IINCHIP_WRITE((SIPR0 + 3),addr[3]);
603	}
604
605
606	/**
607	@brief This function gets Interrupt register in common register.
608	*/
609	uint8 getIR( void )
610	{
611	return IINCHIP_READ(IR);
612	}
613
614
615
616	/**
617	@brief This function sets up Retransmission time.
618
619	If there is no response from the peer or delay in response then retransmission
620	will be there as per RTR (Retry Time-value Register)setting
621	*/
622	void setRTR(uint16 timeout)
623	{
624	IINCHIP_WRITE(RTR0,(uint8)((timeout & 0xff00) >> 8));
625	IINCHIP_WRITE((RTR0 + 1),(uint8)(timeout & 0x00ff));
626	}
627
628
629	/**
630	@brief This function set the number of Retransmission.
631
632	If there is no response from the peer or delay in response then recorded time
633	as per RTR & RCR register seeting then time out will occur.
634	*/
635	void setRCR(uint8 retry)
636	{
637	IINCHIP_WRITE(RCR,retry);
638	}
639
640
641	/**
642	@brief This function set the interrupt mask Enable/Disable appropriate Interrupt. ('1' : interrupt enable)
643
644	If any bit in IMR is set as '0' then there is not interrupt signal though the bit is
645	set in IR register.
646	*/
647	void setIMR(uint8 mask)
648	{
649	IINCHIP_WRITE(IMR,mask); // must be setted 0x10.
650	}
651
652
653	/**
654	@brief These below functions are used to get the Gateway, SubnetMask
655	and Source Hardware Address (MAC Address) and Source IP address
656	*/
657	void getGAR(uint8 * addr)
658	{
659	addr[0] = IINCHIP_READ(GAR0);
660	addr[1] = IINCHIP_READ(GAR0+1);
661	addr[2] = IINCHIP_READ(GAR0+2);
662	addr[3] = IINCHIP_READ(GAR0+3);
663	}
664	void getSUBR(uint8 * addr)
665	{
666	addr[0] = IINCHIP_READ(SUBR0);
667	addr[1] = IINCHIP_READ(SUBR0+1);
668	addr[2] = IINCHIP_READ(SUBR0+2);
669	addr[3] = IINCHIP_READ(SUBR0+3);
670	}
671	void getSHAR(uint8 * addr)
672	{
673	addr[0] = IINCHIP_READ(SHAR0);
674	addr[1] = IINCHIP_READ(SHAR0+1);
675	addr[2] = IINCHIP_READ(SHAR0+2);
676	addr[3] = IINCHIP_READ(SHAR0+3);
677	addr[4] = IINCHIP_READ(SHAR0+4);
678	addr[5] = IINCHIP_READ(SHAR0+5);
679	}
680	void getSIPR(uint8 * addr)
681	{
682	addr[0] = IINCHIP_READ(SIPR0);
683	addr[1] = IINCHIP_READ(SIPR0+1);
684	addr[2] = IINCHIP_READ(SIPR0+2);
685	addr[3] = IINCHIP_READ(SIPR0+3);
686	}
687
688
689	/**
690	@brief These below functions are used to get the Destination Hardware Address (MAC Address), Destination IP address and Destination Port.
691	*/
692	void getSn_DHAR(SOCKET s, uint8 * addr)
693	{
694	addr[0] = IINCHIP_READ(Sn_DHAR0(s));
695	addr[1] = IINCHIP_READ(Sn_DHAR0(s)+1);
696	addr[2] = IINCHIP_READ(Sn_DHAR0(s)+2);
697	addr[3] = IINCHIP_READ(Sn_DHAR0(s)+3);
698	addr[4] = IINCHIP_READ(Sn_DHAR0(s)+4);
699	addr[5] = IINCHIP_READ(Sn_DHAR0(s)+5);
700	}
701	void setSn_DHAR(SOCKET s, uint8 * addr)
702	{
703	IINCHIP_WRITE((Sn_DHAR0(s) + 0),addr[0]);
704	IINCHIP_WRITE((Sn_DHAR0(s) + 1),addr[1]);
705	IINCHIP_WRITE((Sn_DHAR0(s) + 2),addr[2]);
706	IINCHIP_WRITE((Sn_DHAR0(s) + 3),addr[3]);
707	IINCHIP_WRITE((Sn_DHAR0(s) + 4),addr[4]);
708	IINCHIP_WRITE((Sn_DHAR0(s) + 5),addr[5]);
709	}
710	void getSn_DIPR(SOCKET s, uint8 * addr)
711	{
712	addr[0] = IINCHIP_READ(Sn_DIPR0(s));
713	addr[1] = IINCHIP_READ(Sn_DIPR0(s)+1);
714	addr[2] = IINCHIP_READ(Sn_DIPR0(s)+2);
715	addr[3] = IINCHIP_READ(Sn_DIPR0(s)+3);
716	}
717	void setSn_DIPR(SOCKET s, uint8 * addr)
718	{
719	IINCHIP_WRITE((Sn_DIPR0(s) + 0),addr[0]);
720	IINCHIP_WRITE((Sn_DIPR0(s) + 1),addr[1]);
721	IINCHIP_WRITE((Sn_DIPR0(s) + 2),addr[2]);
722	IINCHIP_WRITE((Sn_DIPR0(s) + 3),addr[3]);
723	}
724	void getSn_DPORT(SOCKET s, uint8 * addr)
725	{
726	addr[0] = IINCHIP_READ(Sn_DPORT0(s));
727	addr[1] = IINCHIP_READ(Sn_DPORT0(s)+1);
728	}
729	void setSn_DPORT(SOCKET s, uint8 * addr)
730	{
731	IINCHIP_WRITE((Sn_DPORT0(s) + 0),addr[0]);
732	IINCHIP_WRITE((Sn_DPORT0(s) + 1),addr[1]);
733	}
734
735
736	/**
737	@brief This sets the maximum segment size of TCP in Active Mode), while in Passive Mode this is set by peer
738	*/
739	void setSn_MSS(SOCKET s, uint16 Sn_MSSR0

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